Case Statement in Verilog

Like C/C++ or any other programming languages, Verilog has case keywords which we can use to describe a hardware or use it in verifying the hardware. First, we'll see how to use this to describe a hardware. Basic building block

Usage

  1. It is used inside the procedural block(always or initial block). Let us remind, the output of the Verilog module must be reg type if output is generated from procedural block no matter if it is a combinational circuit or sequential circuit.
  2. If there is only one statement for a case statement, you can directly write the code and nothing to worry about. If there are multiple statement for case statement, the entire if-else statement must be enclosed within begin and end keyword. It is enclosed in case(condition) and endcase block.

Case condition is the input of the circuit and based on the input, output is assigned values or inputs. Condition can be input coming from outside of the module, output signal generated from inside of the module and it can be output of the register.

NOT Gate

NOT gate has one input and one output. The output is complement of the input or it has two cases. First, if the input is 1, output is 0 and vice versa. Let's write a Verilog code for this.

module not_gate( input a, output reg y ); always @(*)begin case(a) 0: y = 1; 1: y = 0; default: y = 0; endcase end endmodule

You can make any combinational circuit using case statement.

Ex-OR Gate

Let's write Verilog code for Ex-Or gate using if-else statement. We know that it has two input and one output. It has four cases which we can write inside the case block to describe a Ex-Or gate.

module xor_gate( input a,b, output reg y ); always @(*)begin case() 0: y = 0; 1: y = 1; 2: y = 1; 3: y = 0; default y = 0; endcase end endmodule

Multiplexer

We can create combinational circuit using case statement. Multiplexer is the most common used circuit in digital system. Let's start with 2X1 MUX which has three inputs, one is select line and other two are inputs selected by the output based on the select line input. Here, two cases are there. First, for select line 0, output is first input and second input is the output for second case. Let's write Verilog code for this.

module mux_2x1( input i0,i0,s, output reg y ); always @(*)begin case(s) 0: y = i0; 1: y = i1; default: y = 0; endcase end endmodule

you can describe combinational and sequential circuit using case statement. You can also use this for describing finite state machine. We'll learn more about this is upcoming articles.

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